a) Field of the Invention
The invention relates to a process for managing exchanges between electronic memories in an information system, as well as to an information system, a memory and a recording medium which implement this process. The invention applies more specifically to multiprocessor information systems with memories that are logically shared and/or physically distributed.
b) Description of Related Art
An information system is constituted by a central subsystem which can communicate with one or more peripheral subsystems by means of input-output units. The central subsystem in a large system ordinarily includes several processors linked to a central memory and to the input-output units.
The function of each processor is the execution of the instructions of the programs contained in the central memory. These instructions and the data necessary for their execution can be accessed by the processor by using the addressing means of the central memory. However, taking into account the relatively long access times in the central memory, the processors are usually equipped with a cache memory which is much faster but whose contents are limited to a certain number of extracts from the contents of the central memory. For example, the central memory is constituted by memory elements, each of which is ordinarily made from an integrated dynamic memory circuit or DRAM (Dynamic Random Access Memory) with 16 megabits, for example, which presently takes about 60 nanoseconds to access a bit, while the cache memory is currently made from a static random access memory (SRAM) which requires on the order of 10 nanoseconds to access a bit. A cache memory is composed of a data memory and a mechanism for managing the addresses of data in the memory. The data memory of a cache memory is divided into memory blocks of the same predetermined size, each of which corresponds to a quantum of exchange with the central memory. A memory block is therefore a logical entity defined by a structure which essentially comprises an address part and a part reserved for the data. Each block is therefore identified by its address, whereas the specific contents of a memory block constitute a copy of it. In other words, each block is made up of one or more copies. A cache memory can be an associative type with a single level, better known as "direct mapped cache memory" or an associative type with several levels. In a cache memory, the mechanism for managing addresses is currently called a directory or "cache tags."
A processor is composed of various processing circuits. An example of a description of these circuits adapted to a microprogrammed processor will be found in the Applicant's patent application EP-A-0434483 (corresponding to U.S. Pat. No. 5,408,623). In this document, the processors are connected by means of their cache memory to a bus which allows them to communicate with the central memory. Each processor and its cache memory resides together on the same printed circuit board which links several integrated circuit packages. Today, the ever-increasing scale of integration makes it possible to integrate each processor in a chip and to associate it with at least one part of the cache memory.
Current advanced information systems interpose other memory levels between the memory and the cache memory of the processor. For example, an intermediate cache memory is used as described in the above-mentioned patent. In this patent, the cache memories near the processors communicate with the central memory through an intermediate cache memory. The cache memories near the processors are therefore called private cache memories and they share the intermediate cache memory, which is therefore called a shared cache memory. A private cache memory is also composed of a data memory and an address management mechanism. More generally, a more or less complex hierarchy can exist between the memories which link a processor to a central memory. In this hierarchy, it is said that the level is higher when it is nearer to the processor. On the other hand, the central memory, which constitutes the lowest level, can also be shared and its elements can be distributed in the information system. The invention generally applies to the management of exchanges between two levels of any hierarchy of electronic memories in an information system.